1. Field of the Invention
The present invention relates to the field of fabrication of integrated circuits, and, more particularly, to filling openings, such as trenches, with an insulating material to thereby form, for example, shallow trench isolation structures required in sophisticated integrated circuits.
2. Description of the Related Art
Modern integrated circuits comprise a huge number of circuit elements, such as resistors, capacitors, transistors and the like. Typically, these circuit elements are formed on and in a semiconductor layer, such as a silicon layer, wherein it is usually necessary to substantially electrically insulate adjacent semiconductor regions from each other, in which the individual circuit elements are formed. A representative example in this respect is a field effect transistor, the active area of which, i.e., the highly doped drain and source regions with an inversely lightly doped channel region disposed therebetween, is defined by an isolation structure formed in the semiconductor material.
Since critical feature sizes of the circuit elements, such as the gate length of field effect transistors, are steadily decreasing, the area enclosed by the isolation structures, as well as the isolation structures themselves, are also reduced in size. Among the various techniques for forming the isolation structures, the so-called shallow trench isolation (STI) technique has proven to be the most reliable method and has become the most frequently used technique for forming isolation structures for sophisticated integrated circuits.
According to the STI technique, individual circuit elements are insulated from each other by shallow trenches etched into the semiconductor material, i.e., a semiconductor substrate when bulk semiconductor devices are considered or a semiconductor layer formed on an insulating substrate as in the case, for example, for silicon-on-insulator (SOI) substrates, in which the circuit elements are to be formed. The trenches are subsequently filled with a dielectric material, such as an oxide, to provide the required electrical insulation of adjacent circuit elements. Although this technique has proven to be very reliable for the dimensions of trenches on the order of micrometers, reliability problems, such as increased leakage currents and the like, may arise for devices defined by sub-micron design rules, as will be explained in the following in more detail.
With reference to FIGS. 1a-1f, a typical conventional process flow for forming a shallow trench isolation will now be described. In FIG. 1a, a semiconductor structure 100 comprises a substrate 101 that may include a semiconductor layer or that may be a semiconductor substrate, such as a silicon substrate, in and on which circuit elements, such as field effect transistors and the like, have to be formed. Moreover, a silicon dioxide layer 102 is formed on the substrate 101 followed by a silicon nitride layer 103.
Typically, the silicon dioxide layer 102 is formed by thermally oxidizing the substrate 101 and, subsequently, the silicon nitride layer 103 is deposited by, for example, chemical vapor deposition (CVD), such as low pressure CVD (LPCVD). Subsequently, a layer of photoresist (not shown) is applied to the semiconductor structure 100 and is patterned by sophisticated photolithography and etch techniques in accordance with design requirements. In the example described herein, the trench isolation to be formed may be designed to have a width on the order of 0.25 xcexcm or less and the photoresist layer is correspondingly patterned to serve as an etch mask for a subsequently performed anisotropic etch step.
FIG. 1b schematically shows the semiconductor structure 100 with a trench 104 formed in the silicon nitride layer 103, the silicon dioxide layer 102 and partially in the substrate 101. Typically, the trench 104 is etched with a depth of approximately 400-500 nm for the above specified width. Moreover, preferably, the anisotropic etch step for etching the silicon nitride layer 103 is designed to generate a tapered sidewall portion 105 that may promote the fill capability of a subsequent deposition step.
FIG. 1c schematically shows the semiconductor structure 100 during an initial stage of a deposition step to fill the trench 104 with silicon dioxide. In FIG. 1c, a relatively thin silicon dioxide layer 106 is already formed on the silicon nitride layer 103 and inside the trench 104. For depositing the silicon dioxide layer 106 into the trench 104 having dimensions of 0.25 xcexcm and less, sophisticated deposition techniques have to be used to achieve a high degree of fullness in the trench 104. Preferably, sub-atmospheric CVD deposition techniques are used for filling trenches having a width of 0.25 xcexcm and sophisticated high density plasma-enhanced CVD deposition techniques may be used for a trench width less than 0.25 xcexcm. Although these deposition techniques allow oncoming particles 107 to be deposited in a highly conformal manner within the trench 104, the upper sidewall portions 105, even though slightly tapered, will receive a thicker silicon dioxide layer during the ongoing deposition, since the number of oncoming particles 107 at corner portions 108 is higher than the number of particles 107 impinging on central sidewall portions 112 of the trench 104.
FIG. 1d illustrates this situation, when the thickness of the silicon dioxide layer 106 has increased during the deposition so that the trench 104 is nearly closed at the corner portions 108, thereby substantially preventing any further deposition of silicon dioxide within the trench 104.
FIG. 1e schematically depicts the semiconductor structure 100 after completion of the deposition step, wherein a void 109 is formed within the trench 104. Since the void 109 is highly undesirable for further processing of the semiconductor structure 100, great efforts are made to at least reduce the size of the void 109. To this end, the semiconductor structure 100 is heated in an oxidizing ambient to a temperature of approximately 900xc2x0 C. to, on the one hand, to densify the silicon dioxide layer 106 and, on the other hand, to further oxidize silicon at the interface between the trench 104 and the substrate 101, as indicated by the layer 110. During this heat treatment, oxygen diffuses into the silicon dioxide layer 106 and thus into the trench 104 and leads to a further oxidation of the substrate 101. Upon oxidation of the substrate 101, stress is applied to the deposited silicon dioxide layer 106 within the trench 104, since the newly grown silicon dioxide adjacent to the deposited silicon dioxide 106 occupies a larger volume than the silicon consumed by the oxidation process. In FIG. 1e, the additional oxidized portion is indicated by 110 and the induced stress is indicated by arrows 111.
FIG. 1f schematically depicts the semiconductor structure 100 after completion of the thermal oxidation process, wherein the void 109 in the lower portion of the trench 104 is removed by compressing the silicon dioxide 106, so that a considerably smaller void 109a is formed in the vicinity of the upper portion of the trench 104. As is evident from FIG. 1f, substantially no stress is generated at the upper sidewall portions 105 of the non-oxidizable silicon dioxide layer 102 and the silicon nitride layer 103.
FIG. 1g schematically shows the semiconductor structure 100 after planarizing the substrate 101 by chemically mechanically polishing (CMP) to remove the excess silicon dioxide 106 and partially remove the silicon nitride layer 103, wherein the reduced void 109a is opening to form a groove-like recess that is, for convenience, also denoted by the reference number 109a. The CMP process for removing the excess oxide 106 and planarizing the substrate 101 is a critical step requiring thorough control of the remaining silicon nitride layer 103, since any over-polish of the silicon nitride layer 103 may result in damage of the under-lying silicon of the substrate 101, which represents the active area for the formation of circuit elements such as field effect transistors, thereby compromising the quality of these elements. An xe2x80x9cunder-polishxe2x80x9d of the excess silicon dioxide layer 106 and the underlying silicon nitride layer 103, on the other hand, may significantly adversely affect a subsequent sophisticated photolithography step required for the formation of gate electrodes of the field effect transistors. Consequently, avoiding an opening of the reduced void 109a during the CMP or substantially removing the reduced void 109a by over-polishing would be extremely difficult to achieve without imparting a high risk for subsequent process steps.
FIG. 1h schematically shows the semiconductor structure 100 after removing the silicon nitride layer 103 and the silicon dioxide layer 102. Typically, these layers are removed by etch processes well known in the art, during which the silicon dioxide 106 in the trench 104 is also partially removed, as indicated by 113, and the size of the recess 109a is further increased. Moreover, the size of the recess 109a may be even further increased by subsequent process steps, such as any clean processes prior to forming a gate insulation layer for any field effect transistors to be formed on the substrate 101.
The recess 109a may represent a source of reduced reliability for circuit elements, such as field effect transistors, since, for example, gate electrode material frequently provided as polysilicon may not be efficiently removed from the recess 109a during the patterning of the gate electrode of the field effect transistors. Thus, an increased leakage current or even short circuits between unrelated gate electrodes may occur, thereby significantly deteriorating production yield.
Since the problems identified above represent a serious drawback for semiconductor technologies, such as CMOS technology, especially if based on sub-0.25 micron design rules, there exists a need for a process technique allowing the filling of openings, such as trenches, with a dielectric material substantially without generating any voids.
In general, the present invention is directed to a method allowing openings or recessed portions, such as trenches used for isolation structures, to be filled with a dielectric material, wherein the formation of voids may be substantially avoided by creating a stress to the deposited dielectric material substantially along the entire depth of the recessed portion. This is achieved by depositing a layer of oxidizable material in the recessed portion, thereby covering the inner sidewalls of the recessed portion prior to filling in the dielectric material. In a subsequent oxidation process, the oxidizable material is oxidized and exerts stress to the dielectric material along substantially the entire depth of the recessed portion, irrespective whether initially sidewall portions of the recessed portion comprise any non-oxidizable areas.
According to one illustrative embodiment of the present invention, a method of filling a trench formed in a substrate comprises conformally depositing a spacer layer comprised of oxidizible material on the substrate and in the trench. Then, a dielectric material is deposited over the spacer layer to fill the trench and an oxidation process in an oxidizing ambient is carried out to convert at least a portion of the spacer layer into an insulating layer.
According to a further illustrative embodiment of the present invention, a method of filling a trench formed in a substrate with a dielectric material comprises forming spacer elements on sidewalls of the trench, wherein the spacer elements are comprised of an oxidizable material. Next, a dielectric material is deposited over the substrate to substantially fill the trench and the substrate is exposed to an oxidizing ambient to convert the spacer elements at least partially into an insulating layer.
According to yet another illustrative embodiment of the present invention, a method of filling a trench in a substrate comprising a layer of a semiconductive material and a layer of a dielectric material formed thereon comprises forming sidewall spacers of a semiconductive material in the trench, wherein the sidewall spacers cover non-oxidizable sidewall portions of the trench. Then, the trench is filled with a dielectric material and the substrate is exposed to an oxidizing ambient to at least partially oxidize the sidewall spacers.
In accordance with still another illustrative embodiment of the present invention, a method of forming an isolation structure in a substrate comprising a semiconductive layer and a dielectric layer stack formed on the semiconductive layer comprises forming a trench in the substrate, wherein the trench extends in a depth dimension through the dielectric layer stack. A spacer layer is conformally deposited on the substrate, whereby the spacer layer is comprised of an oxidizable material. Next, a dielectric material for filling the trench is deposited and the substrate is exposed to an oxidizing ambient to at least partially oxidize the spacer layer to fill any void that may have formed during deposition of the dielectric material.
In a further embodiment of the present invention, a method of forming shallow trench isolation structures in a substrate of a semiconductive material during a manufacturing process for manufacturing integrated circuits comprises forming a first layer of dielectric material on the substrate of semiconductive material. Then, the first layer of dielectric material and the substrate of semiconductive material are selectively etched so as to form trenches deeper than the thickness of the layer of dielectric material. Sidewall spacers of a semiconductive material are formed in the trenches, wherein the sidewall spacers cover the inside sidewalls of the trenches. Thereafter, the trenches are filled with a dielectric material and the sidewall spacers are oxidized along the entire depth of the trench sidewalls.